- 仕様
- ピン配置
- 外形図
- 絶対最大定格
- 電気特性
| 項目 | 仕様 | 単位 |
|---|---|---|
| 構造 | COF + FR + PCB | |
| サイズ(対角線) | 2.8 | インチ |
| ドットマトリックス / 解像度 | 256 × 64 | ドット |
| モジュール寸法 | 85.0 × 39.8 × 7.83 | mm |
| ビューイングエリア(VA) | 71.1 × 19.26 | mm |
| アクティブエリア(AA) | 69.1 × 17.26 | mm |
| ドットサイズ | 0.248 × 0.248 | mm |
| ドットピッチ | 0.27 × 0.27 | mm |
| 表示色 | OLED, 白色 / 黄色 | |
| グレースケールをサポートする | あり | |
| ディスプレモード | パッシブマトリクス | |
| IC | SSD1322 (COF) | |
| インターフェス | 6800,8080,SPI | |
| PCAP IC | FT6336U | |
| PCAP インターフェス | I2C | |
| 入力ポイント | 1 | Points |
| タッチパネル | 静電容量式タッチパネル | |
| 表面 | グレア | |
| 供給電圧 | 3V | |
| Duty | 1/64 Duty | |
| 操作温度 | -20~+70 | °C |
| 保存温度 | -30~+80 | °C |
| タイプ | グラフィック型 OLED モジュール , タッチパネル付き OLED モジュール |
| Pin Number | 記号 | I/O | 功能 | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | VSS | P | Ground. | ||||||||||
| 2 | VDD | P | Power Supply for Core Logic Circuit Power supply pin for core logic operation. A capacitor is required to connect between this pin and VSS |
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| 3 | N.C. | P | Reserved Pin The N.C. pin between function pins are reserved for compatible and flexible design. |
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| 4 | D/C# | I | Data/Command Control This pin is Data/Command control pin connecting to the MCU. When the pin is pulled HIGH, the content at D[7:0] will be interpreted as data. When the pin is pulled LOW, the content at D[7:0] will be interpreted as command. |
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| 5 | R/W# (WR#) |
I | Read/Write Select or Write This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull this pin to “High” for read mode and pull it to “Low” for write mode. When 80XX interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the CS# is pulled low. When serial mode is selected, this pin must be connected to VSS. |
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| 6 | E/RD# | I | Read/Write Enable or Read This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the CS# is pulled low. When connecting to an 80XX-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and CS# is pulled low. When serial mode is selected, this pin must be connected to VSS. |
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| 7~14 | DB0 | I/O | Host Data Input/Output Bus These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial mode is selected, D1 will be the serial data input SDIN and D0 will be the serial clock input SCLK. |
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| DB1 | |||||||||||||
| DB2 | |||||||||||||
| DB3 | |||||||||||||
| DB4 | |||||||||||||
| DB5 | |||||||||||||
| DB6 | |||||||||||||
| DB7 | |||||||||||||
| 15 | NC | P | Reserved Pin The N.C. pin between function pins are reserved for compatible and flexible design. |
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| 16 | RES# | I | This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is executed. Keep this pin pull HIGH during normal operation. |
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| 17 | CS# | I | Data/Command Control This pin is the chip select input connecting to the MCU. The chip is enabled for MCU communication only when CS# is pulled LOW. |
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| 18 | NC | P | Reserved Pin The N.C. pin between function pins are reserved for compatible and flexible design. |
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| 19 | BS1 | I | Communicating Protocol Select These pins are MCU interface selection input. See the following table:
Note (1) 0 is connected to VSS (2) 1 is connected to VDD |
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| 20 | BS0 | ||||||||||||
| 21 | TP_SCK | I | I2C clock input | ||||||||||
| 22 | TP_SDA | I | I2C data input and output | ||||||||||
| 23 | TP_INT | I | External interrupt to the host | ||||||||||
| 24 | TP_RST | I | External Reset, Low is active |
| パラメーター | 記号 | 最小値 | 最大値 | 単位 |
|---|---|---|---|---|
| Supply Voltage for Display | VDD | -0.3 | 4 | V |
| 操作温度 | TOP | -20 | +70 | °C |
| 保存温度 | TSTG | -30 | +80 | °C |
DC 電気特性
| 項目 | 記号 | 条件 | 最小値 | 典型値 | 最大値 | 単位 |
|---|---|---|---|---|---|---|
| Supply Voltage for Logic | VDD | － | 2.8 | 3.0 | 3.3 | V |
| High Level Input | VIH | － | 0.8×VDD | － | VDD | V |
| Low Level Input | VIL | － | 0 | － | 0.2×VDD | V |
| High Level Output | VOH | － | 0.9×VDD | － | VDD | V |
| Low Level Output | VOL | － | 0 | － | 0.1×VDD | V |
| 50% Check Board operating Current | VDD =3V | － | 125 | 250 | mA | |
